The trend for semiconductor devices is smaller integrated circuit (IC) devices (also referred to as chips), packaged in smaller packages (which protect the chip while providing off chip signaling connectivity). One example are image sensors, which are IC devices that include photo-detectors which transform incident light into electrical signals (that accurately reflect the intensity and color information of the incident light with good spatial resolution).
There are different driving forces behind the development of wafer level packaging solutions for image sensors. For example, reduced form factor (i.e. increased density for achieving the highest capacity/volume ratio) overcomes space limitations and enables smaller camera module solutions. Increased electrical performance can be achieved with shorter interconnect lengths, which improves electrical performance and thus device speed, and which strongly reduces chip power consumption. Heterogeneous integration allows for the integration of different functional layers (e.g. the integration of high and low resolution images sensors, the integration of the image sensor with its processor, etc.). Cost reductions per unit packaging can be achieved by packaging only those chips that are known to be good (i.e. only packaging Known Good Dies—KGD).
Presently, chip-on-board (COB—where the bare chip is mounted directly on a printed circuit board) and Shellcase Wafer Level CSP (where the wafer is laminated between two sheets of glass) are the dominant packaging and assembly processes used to build image sensor modules (e.g. for mobile device cameras, optical mice, etc.). However, as higher pixel image sensors are used, COB and Shellcase WLCSP assembly becomes increasingly difficult due to assembly limitations, size limitations (the demand is for lower profile devices), yield problems and the capital investment for packaging 8 and 12 inch image sensor wafers. For example, the Shellcase WLCSP technique involves packaging the image sensors on the wafer before the wafer is singulated into separate packaged chips, meaning that those chips from each wafer that are defective are still packaged before they can be tested (which drives up the cost). Additionally, standard WLP packages are fan-in packages, in which chip area is equal to the package area, thus limiting the number of I/O connections. Lastly, standard WLP package are bare die packages, which can be complex in test handling, assembly and SMT.
There is a need for an improved package and packaging technique for chips such as image sensor chips that have already been singulated and tested, and provide a low profile packaging solution that is cost effective and reliable (i.e. provides the requisite mechanical support and electrical connectivity).